Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, known as a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. An FPGA may also include various dedicated logic circuits, such as memories, digital clock managers (DCMs), and input/output (I/O) transceivers. Notably, an FPGA may include one or more embedded processors. The programmable logic of an FPGA (e.g., CLBs, IOBs, and interconnect structure) is typically programmed by loading a stream of configuration data (known as a bitstream) into internal configuration memory cells. The states of the configuration memory cells define how the CLBs, IOBs, interconnect structure, and other programmable logic are configured. Some FPGAs include support for run-time partial reconfiguration, which provides the ability to alter the behavior of portions of a circuit configured in an active FPGA. Partial reconfiguration is useful in systems that must support a wide range of optional behavior, only a subset of which is operational at any point in time.
FPGAs are suited for implementing circuits to process various types of content, such as compressed digital video data (moving picture experts group (MPEG) video streams), audio, multimedia, imaging, or the like. The latest trend in video coding is to provide various forms of scalability, sometimes all embodied within the same compressed video bitstream. Typically, this compressed data is provided in the form of a “base layer,” as well as one or more “enhancement layers.” A decoder system would be capable of creating a valid video output using just the base layer or the base layer and any combination of the enhancement layers. Exemplary types of scalability provided in the enhancement layers include: temporal scalability (i.e., frame rate), quality scalability (i.e., often measured by peak signal-to-noise ratio), and resolution scalability (i.e., frame size).
An example of this type of coder/decoder (codec) is embodied in the scalable video coding (SVC) development work currently ongoing under the auspices of the MPEG standards committee and the ISO/IEC Joint Video Team (JVT). SVC is an extension to the MPEG-4 Advanced Video Coding (AVC) standard (also known as MPEG-4, Part 10) jointly developed by the International Organization for Standardization (ISO) and International Telecommunication Union (ITU-T). The MPEG-4 AVC standard is published as ITU-T H.264 and ISO/IEC 14496-10. The proposed SVC codec provides all three of the aforementioned types of scalability (e.g., temporal, quality, and resolution) in labeled packets within the same bitstream. Either a smart network can be used to decide which types of packets to send to a particular end-user, or the end-user can receive the entire bitstream and only decode the packets that her or she is capable (authorized) of decoding.
One technique for providing the capability to process all layers in scalable content is to employ dedicated circuitry for processing the base layer and each possible enhancement layer. Thus, the decoder includes enhancement layer circuitry even if the end-user is not authorized to process certain enhancement layer(s), which impacts security. Accordingly, there exists a need in the art for a method and apparatus for processing scalable content that exhibits increased security.